ADSP-2186 |
RFQ for ADSP-2186 Required Field |
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| Technical/Catalog Information | ADSP-2186BST-115 |
| Vendor | Analog Devices Inc |
| Category | Integrated Circuits (ICs) |
| Package / Case | 100-LQFP |
| Packaging | Tray |
| Type | Fixed Point |
| Non-Volatile Memory | External |
| On-Chip RAM | 40kB |
| Interface | Host Interface, Serial Port |
| Voltage - I/O | 5.00V |
| Voltage - Core | 5.00V |
| Clock Rate | 28.8MHz |
| Operating Temperature | -40°C ~ 85°C |
| RoHS Status | RoHS Non-Compliant |
| Other Names | ADSP 2186BST 115 ADSP2186BST115 |
| Product | Manufacturers | Pack | D/C |
| ADSP-2186 | - | QFP | - |
The ADSP-2186 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.
The ADSP-2186 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory.
The ADSP-2186 integrates 40K bytes of on-chip memory configured as 8K words (24-bit) of program RAM and 8K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment.
The ADSP-2186 is available in 100-lead LQFP and 144-Ball Mini-BGA packages.
In addition, the ADSP-2186 supports new instructions, which include bit manipulations-bit set, bit clear, bit toggle, bit test-new ALU constants, new multiplication instruction (x squared),biased rounding, result free ALU operations, I/O memory transICE-fers and global interrupt masking for increased flexibility.
Features |
| PERFORMANCE25 ns Instruction Cycle Time 40 MIPS SustainedPerformanceSingle-Cycle Instruction ExecutionSingle-Cycle Context Switch3-Bus Architecture Allows Dual Operand Fetches inEvery Instruction CycleMultifunction InstructionsPower-Down Mode Featuring Low CMOS StandbyPower Dissipation with 100 Cycle Recovery fromPower-Down ConditionLow Power Dissipation in Idle ModeINTEGRATIONADSP-2100 Family Code Compatible, with InstructionSet Extensions40K Bytes of On-Chip RAM, Configured as8K Words On-Chip Program Memory RAM and8K Words On-Chip Data Memory RAMDual Purpose Program Memory for Both Instructionand Data StorageIndependent ALU, Multiplier/Accumulator and BarrelShifter Computational UnitsTwo Independent Data Address GeneratorsPowerful Program Sequencer ProvidesZero Overhead Looping Conditional InstructionExecutionProgrammable 16-Bit Interval Timer with Prescaler100-Lead LQFP144-Ball Mini-BGASYSTEM INTERFACE16-Bit Internal DMA Port for High Speed Access toOn-Chip Memory (Mode Selectable)4 MByte Byte Memory Interface for Storage of DataTables and Program Overlays8-Bit DMA to Byte Memory for Transparent Programand Data Memory Transfers (Mode Selectable)I/O Memory Interface with 2048 Locations SupportsParallel Peripherals (Mode Selectable)Programmable Memory Strobe and Separate I/O MemorySpace Permits "Glueless" System Design(Mode Selectable)Programmable Wait State GenerationTwo Double-Buffered Serial Ports with CompandingHardware and Automatic Data BufferingAutomatic Booting of On-Chip Program Memory fromByte-Wide External Memory, e.g., EPROM, orThrough Internal DMA PortSix External Interrupts13 Programmable Flag Pins Provide Flexible SystemSignalingUART Emulation through Software SPORT ReconfigurationICE-Port™ Emulator Inter |
